V-Tec AT16/C5 Spécifications Page 28
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- Table des matières
- MARQUE LIVRES
Noté. / 5. Basé sur avis des utilisateurs
Si2400
28 Rev. 1.3
5.16. Clock Generation Subsystem
The Si2400 contains an on-chip clock generator. Using
a single master clock input, the Si2400 can generate all
modem sample rates necessary to support V.22bis,
V.22/Bell212A, and V.21/Bell103 standards and a
9.6 kHz rate for audio playback. Either a 4.9152 MHz
clock on XTALI or a 4.9152 MHz crystal across XTALI
and XTALO form the master clock for the Si2400. This
clock source is sent to an internal phase-locked loop
(PLL) which generates all necessary internal system
clocks. The PLL has a settling time of ~1 ms. Data on
RXD should not be sent to the device prior to settling of
the PLL.
The CLKOUT pin outputs a 78.6432 MHz/(N + 1) clock
which may be used to clock a microcontroller or other
devices in the system. N may be programmed via
SE1[4:0] (CLKD) to any value from 1 to 31. N defaults to
7 on power-up. CLKOUT is disabled by setting N = 0.
SE1[7:6] (MCKR) allows the user to control the
microcontroller clock rate. On powerup, the Si2400
UART DTE rate is set to 2400 bps, given that the clock
input is 4.9152 MHz. The MCKR register conserves
power via slower clocking of the microcontroller for
specific applications where power conservation is
required. Table 16 shows the configurations for different
values of MCKR.
Table 15. Handshaking Control Registers
Register Name Function Units Default
S1E TATL Transmit Answer Tone Length 1 sec 0x03
S1F ATTD Answer Tone to Transmit Delay 5/3 msec 0x2D
S20 UNL Unscrambled Ones Length—V.22 5/3 msec 0x5D
S21 TSOD Transmit Scrambled Ones Delay—V.22 53.3 msec 0x09
S22 TSOL Transmit Scrambled Ones Length—V.22 5/3 msec 0xA2
S23 VDDL V.22/22b Data Delay Low 5/3 msec 0xCB
S24 VDDH V.22/22b Data Delay High (256) 5/3 msec 0x08
S25 SPTL S1 Pattern Time Length V.22b 5/3 msec 0x3C
S26 VTSO V.22b 1200 bps Scrambled Ones Length 53.3 msec 0x0C
S27 VTSOL V.22b 2400 bps Scrambled Ones Length Low 5/3 msec 0x78
S28 VTSOH V.22b 2400 bps Scrambled Ones Length High (256) 5/3 msec 0x08
S2A RSO Receive Scrambled Ones V.22b Length 5/3 msec 0xD2
S2F FCD FSK Connection Delay Low 5/3 msec 0x3C
S30 FCDH FSK Connection Delay High (256) 5/3 msec 0x00
S31 RATL Receive Answer Tone Length 5/3 msec 0x3C
S34 TASL Answer Tone Length (only used in S1E [TATL] = 0x00) 5/3 msec 0x5A
S35 RSOL Receive V.22 Scrambled Ones Length 5/3 msec 0xA2
Table 16. MCKR Configurations
SE1[7:6]
(MCKR)
Controller
Clock (MHz)
Modes
0 0 9.8304 MHz
All (default)
0 1 4.9152 MHz All except V.22bis,
PCM
1 0 2.4576 MHz Command only
1 1 Reserved Reserved
- Features 1
- Applications 1
- Description 1
- Functional Block Diagram 1
- 2 Rev. 1.3 2
- TABLE OF CONTENTS 3
- 1. Electrical Specifications 4
- Table 2. Loop Characteristics 5
- Table 3. DC Characteristics 6
- Table 4. DC Characteristics 6
- Table 5. AC Characteristics 7
- for K-Grade, T 8
- –40 to 85°C for B-Grade) 8
- = –40 to 85°C for B-Grade) 9
- 10 Rev. 1.3 10
- 3. Bill of Materials 11
- 12 Rev. 1.3 12
- 4. Analog Input/Output 13
- 5. Functional Description 14
- 5.1. Digital Interface 15
- 16 Rev. 1.3 16
- 5.3. Low Power Modes 17
- 5.4. Global DAA Operation 17
- 18 Rev. 1.3 18
- Rev. 1.3 19 19
- 20 Rev. 1.3 20
- 5.6. Loop Current Detection 21
- 5.7. Carrier Detect/Loss 21
- 5.8. Overcurrent Detection 21
- 5.11. PCM Data Mode 23
- Figure 10. Signal Routing 24
- 5.12. Analog Codec 25
- 5.14. V.42 HDLC Mode 26
- 5.15. Fast Connect 27
- Table 16. MCKR Configurations 28
- 6.1. Command Line Execution 29
- 30 Rev. 1.3 30
- 6.4. S-Register Control 31
- 32 Rev. 1.3 32
- 6.5.4. A1 34
- 6.5.5. !2 34
- 6.5.6. !7 34
- Table 19. !7 Parameters 35
- Figure 12. !7 Security Timing 36
- Progress 37
- S19 S1A S1B S16 S17 S18 38
- Table 23. DTMF 39
- 7.1. DSP Registers 40
- SE8 SE6 SE5 41
- DSP Reg. Addr 41
- 7.2. Call Progress Filters 42
- 8. S Registers 43
- 44 Rev. 1.3 44
- Rev. 1.3 45 45
- 46 Rev. 1.3 46
- Rev. 1.3 47 47
- 50 Rev. 1.3 50
- Rev. 1.3 51 51
- 52 Rev. 1.3 52
- Rev. 1.3 53 53
- 54 Rev. 1.3 54
- Rev. 1.3 55 55
- 56 Rev. 1.3 56
- 58 Rev. 1.3 58
- Kissoff Tone Detect Length) 58
- Rev. 1.3 59 59
- 60 Rev. 1.3 60
- Rev. 1.3 61 61
- 62 Rev. 1.3 62
- Rev. 1.3 63 63
- Rev. 1.3 65 65
- 66 Rev. 1.3 66
- Rev. 1.3 69 69
- 70 Rev. 1.3 70
- Rev. 1.3 71 71
- 72 Rev. 1.3 72
- Rev. 1.3 73 73
- 74 Rev. 1.3 74
- Rev. 1.3 75 75
- 76 Rev. 1.3 76
- Rev. 1.3 77 77
- DAA Isolation Barrier 78
- Emissions/Immunity 78
- DC Termination 79
- AC Termination 80
- Ringer Impedance 80
- DTMF Dialing 80
- Pulse Dialing 80
- Billing Tone Detection 80
- Symbol Value 81
- In-Circuit Testing 82
- Compliance Test Commands 83
- Introduction 84
- APPENDIX C—UL1950 3RD EDITION 85
- 9. Pin Descriptions: Si2400 86
- Rev. 1.3 87 87
- 10. Pin Descriptions: Si3015 88
- Receive Input 89
- Filter 2 89
- Pin # Pin Name Description 89
- 11. Ordering Guide 90
- Millimeters 91
- Revision 1.1 to Revision 1.2 92
- Revision 1.2 to Revision 1.3 92
- Rev. 1.3 93 93
- CONTACT INFORMATION 94
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